Debugging the Localization Bugs and Improve Microprocessor Performance Using Machine Learning

Processor design evaluation and debugging are challenging and complex tasks that take up the majority of the design process as well as require significant engineering resources. The performance of overall processor gets reduced because of bugs with no effect of the functionality are especially challenging for debugging owing to the lack of a universal standard from bug-free performance. This is due to the functional errors, the optimum processor performance for novel microarchitectures on complicated whereas the benchmark of long-run is usually predictably determined. To solve the mentioned problems, we are presenting a Machine Learning (ML) approach that is Deep Neural Network (DNN) with Improved Firefly Algorithm (IFA) as DNN-IFA as a classifier for performance benchmarking of new microarchitectures. The performance of a novel microarchitecture may be assumed to be appropriate if the present microarchitecture outperforms the preceding generation, despite considerable performance regressions in the initial implementation. Moreover, this proposal has influences hyperparamer and by modifying the feature fitness of firefly algorithm resulted to improve the fitness by avoiding bias has capability in detecting the bug performance endurance in microprocessors. The findings reveal that the most effective technique discovers microprocessor core performance defect is 91.5% with a standard IPC impact of more than 1% across the analyzed applications, compared to a bug-free design with no instances of false positives. The suggested system in the simulated scenario takes consumes less time to execute a bug location inference that resulted to minimize the debugging time.