Wafer-Scale Monolithic 3D Integration of CMOS Logic Gates Based on 2D Materials

Monolithic three-dimensional (M3D) integration offers a promising path to enhance transistor density and energy efficiency in next-generation electronics. In this work, we explore the 8 -inch wafer-scale integration of complementary metal-oxide-semiconductor (CMOS) logic gates, including inverters, and NAND gates using two-dimensional materials (2DMs), specifically molybdenum disulfide <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\left(\text{MoS}_{2}\right)$</tex> and tungsten diselenide (<tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\text{WSe}_{2}$</tex>). By vertically stacking <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\text{MoS}_{2}$</tex>-based N-channel MOS (NMOS) and WSe <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">${ }_{2}$</tex>-based P-channel MOS (PMOS) field-effect transistors (FETs), we demonstrate a high-performance CMOS inverter with a voltage gain of 60 at a Vdd of 2 V.