First Thorough Assessment of Time-Dependent Dielectric Breakdown in Sub-25 nm Gate-All-Around Vertical Ingazno Transistor for 4F² DRAM Application

Degradation mechanisms of scaled InGaZnO vertical channel transistors (VCTs) below <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$25-\text{nm}$</tex> diameter were intensively investigated for the first time. We quantified the effects of hole curvature, hole roughness and process damage on the breakdown property, and identified main cause for reliability degradation. By process optimization dedicated to the vertical gate-all-around (GAA) structure, we achieved the time-dependent dielectric breakdown (TDDB) lifetime of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$&gt;10$</tex> years, comparable to an intrinsic stochastic dielectric breakdown lifetime, making it promising for future reliable <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$4 ~\mathrm{F}^{2}$</tex> DRAM application.