Wide Memory Window and Steep ISPP Slope (13.2 V and 2.7) of an Aggressively Scaled 3D Ferroelectric NAND (Fenand) Cell for lt;30\text{nm}$ Tier Pitch Scaling

This study demonstrates a maximum memory window (MW) of 13.2 V and an average ISPP slope of 2.7, achieving the bestreported performance obtained in vertical Gate-All-Around (GAA) 3D FeNAND architecture. The device features a 20 nm gate length (<tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{L}_{\mathrm{G}}$</tex>) and a 42 nm layer pitch. These achievements were made possible through significant innovations in gate stack engineering. The roles of channel interlayer (CIL) and ferroelectric (FE) switching, identified as primary limiters for optimal MW and reliability, are examined through precise tunneling current and trap emission probability calculations. Retention and endurance characteristics were measured with a large MW of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$&gt;8 ~\mathrm{V}$</tex>. The trade-offs between the initial MW and reliability are discussed. The higher slope of 2.7 enables <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\sim 30 \%$</tex> tier pitch scaling, paving the way for sub-30 nm tier pitch.