High-speed dividing device with the formation of quotient and remainder

Considered the possibility of accelerating the time-critical operation of division for multi-bit integers. This problem is significant since, so multi-bit integers are widely used in specialized devices, including cryptographic transformations. A method for high-speed quotient and remainder determination with optimal hardware costs is proposed. A preliminary increase in the divisor and its subsequent decrease by shifting it to the right are used. A structural diagram and functional diagram of the hardware implementation have been developed using high-speed combinational logic circuits. The device’s principle of operation, its step-by-step process, and specific examples illustrating its correct operation and resource efficiency are addressed. On average, it takes (k/2+1) clock cycles to obtain the result, where (k+1) bit capacity of the quotient. In most division schemes with optimal hardware costs, the number of clock cycles required to obtain the quotient (without remainder) is (k+1). High-speed division with simultaneous determination of several quotient bits requires (m/p) clock cycles for the division operation, where p- the number of simultaneously determined quotient bits, m-bit capacity of dividend. However, this approach will require additional hardware. The research will continue by modeling the device in Vivado Design Suite computer aided design (CAD) based on Artix-7 field programmable gate array (FPGA) from Xilinx.