Optimized Double Tail Comparator based ADC for High Speed and Low Power Applications

Dynamic regenerative comparators are being used to increase speed and power efficiency in response to the need for ultra-low-power, area-efficient, and high-speed analog-to-digital converters. This study suggests using two transistors to create a low power double-tail comparator for the Flash Analog-to-Digital Converter. Designing a comparator and thermometer code to binary code converter at low supply voltage and low power dissipation is a challenging task in the creation of a low power Flash ADC. The primary goal is to construct comparators in order to achieve a high-speed Flash ADC. We should design each comparator to have a lower total power consumption because the comparators in Flash ADC are power-hungry components. Here, a low-power dynamic comparator is being designed. Next, we used a 2:1 MUX based on pass transistor logic to construct an encoder block. We have constructed a 5-bit Flash ADC using these components. To lower the Flash ADC's power consumption, a comparator and encoder are implemented utilizing dynamic CMOS circuitry. The Tanner EDA back-end tool is used to run the simulation.