LLM-driven verification assistance: Bridging code, coverage and collaboration

The integration of Large Language Models (LLMs) into the hardware design verification (DV) landscape represents a pivotal moment in the evolution of verification workflows. LLMs offer powerful capabilities for natural language processing, code generation, and collaborative assistance, allowing them to bridge gaps between code comprehension, coverage analysis, and team communication. This review synthesizes the most recent developments in LLM-driven DV, covering assertion generation, coverage diagnostics, and UVM testbench completion. We propose an architectural model where modular LLM agents act as code analyzers, coverage interpreters, and assertion suggesters, working alongside human engineers. Experimental findings show clear advantages in accuracy, interpretability, and engineering efficiency. We conclude with an analysis of emerging trends and the necessary steps to industrialize LLM adoption in formal verification.