The Impact of Through Silicon Metal (TSM) Contact on Performance and Thermal Reliability in CFET

This work proposes a common-drain engineering technique using Through-Silicon Metal (TSM) to improve electro-thermal performance in CFET architectures. After optimizing the Bottom Dielectric Isolation (BDI) thickness to 5 nm, the TSM-integrated CFET exhibits ~10% reduction in gate capacitance (Cgg : 0.580 → 0.537 fF) and ~12.5% lower nFET thermal resistance (Rth : 0.795 → 0.696 K/μW) compared to the reference. In the TSM structure, although the common drain-to-metal contact area is reduced, SNMR degradation remains minimal (~2 mV). In addition, device lifetime shows significant improvement, with BTI and HCI projections extended by ~2× and ~1.6×, respectively. These results demonstrate that TSM enables effective electro-thermal co-optimization for future CFET logic integration.