Real-Time Simulation Method for High-Frequency Power Electronic Converters With Blocking Mode

For the bridge-based high-frequency power electronic converters (BHPECs) using the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><small>on</small></sub>/<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><small>off</small></sub> model, the identification of blocking mode is crucial for the real-time simulation to avoid oscillation and ensure model accuracy. This article presents a predictive correction method that identifies the blocking mode of the half-bridge arm with low computational amount. The proposed method ensures model stability by the backward Euler method and achieves decoupling between half-bridge arms. Besides, by correcting the predicted state variables at the diode status-changing time point, this method significantly reduces the computational amount compared to the existing blocking mode identification methods without iterative operations. Finally, a series load resonant (SLR) converter with 100 kHz switching frequency and an LLC resonant converter with 200 kHz switching frequency were implemented on a field programmable gate array (FPGA), achieving simulation time steps as low as 20 ns. Comparisons with existing methods confirm the advantages of the proposed method in terms of timing and resource consumption.