Cancellation of Quantization Noise in Sigma Delta Modulators Through Modeling of Non-Linearities

The linearity of Sigma Delta Modulators (SDMs) is typically evaluated by performing a Fourier Transform of the output bitstream. However, the presence of quantization noise in the output bitstream complicates this task: many samples and lengthy simulations are needed to lower this noise floor and evaluate the signal harmonics. We present here a method to estimate the quantization noise in the presence of non-linearity, remove it from the SDM bitstream, and reduce the number of samples needed to quantify the SDM linearity. By applying the proposed technique to a behavioral model of a 4th-order SDM, the accuracy of the linearity estimation is kept unchanged using 5000x less bitstream samples. This in turn can significantly reduce the SDM verification time.

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Publication Details

Journal
IEEE Transactions on Circuits & Systems II Express Briefs
Published
2025-08-04
DOI
https://doi.org/10.1109/tcsii.2025.3594847
Primary Topic
Analog and Mixed-Signal Circuit Design
Type
article
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article

Cancellation of Quantization Noise in Sigma Delta Modulators Through Modeling of Non-Linearities

Stijn Ringeling, Eugenio Cantatore, Lucien J. Breems, Marco Fattori et al.
IEEE Transactions on Circuits & Systems II Express Briefs
Analog and Mixed-Signal Circuit Design
article

Cancellation of Quantization Noise in Sigma Delta Modulators Through Modeling of Non-Linearities

Stijn Ringeling, Eugenio Cantatore, Lucien J. Breems, Marco Fattori, Shagun Bajoria, Robert J. Rutten
article en

Abstract

The linearity of Sigma Delta Modulators (SDMs) is typically evaluated by performing a Fourier Transform of the output bitstream. However, the presence of quantization noise in the output bitstream complicates this task: many samples and lengthy simulations are needed to lower this noise floor and evaluate the signal harmonics. We present here a method to estimate the quantization noise in the presence of non-linearity, remove it from the SDM bitstream, and reduce the number of samples needed to quantify the SDM linearity. By applying the proposed technique to a behavioral model of a 4th-order SDM, the accuracy of the linearity estimation is kept unchanged using 5000x less bitstream samples. This in turn can significantly reduce the SDM verification time.

IEEE Transactions on Circuits & Systems II Express BriefsVol. 72(12)
NXP (Netherlands) (NL), Eindhoven University of Technology (NL)
Affordable and clean energy
Openalex Percentile: Top 82%
Analog and Mixed-Signal Circuit Design
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Cancellation of Quantization Noise in Sigma Delta Modulators Through Modeling of Non-Linearities — Stijn Ringeling, Eugenio Cantatore, et al. · IEEE Transactions on Circuits & Systems II Express Briefs (2025) | TGRS Research Map | TGRS