A Compact <i>D</i> -Band Stacked Power Amplifier With 16.1-dBm <i>P</i> _sat and 636-mW/mm ² Power Density

This letter presents a <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</i>-band power amplifier (PA) fabricated in 40-nm bulk CMOS technology. The proposed design employs a T-model analysis of the internal node between the common-source (CS) and common-gate (CG) transistors in the stacked-FET structure. Based on this analysis, an optimized T-network was implemented to mitigate phase misalignment, resulting in boosted output power and power-added efficiency (PAE). Measurement results demonstrate a saturated output power (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P_{\mathrm {sat}}$</tex-math> </inline-formula>) of 16.1 dBm, peak PAE of 12.5%, and a gain of 32.2 dB, achieving the highest reported power density of 636 mW/mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> among CMOS-based <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</i>-band PAs. It further supports 16-/64-QAM data rates of 16 and 12 Gb/s, respectively.