Investigation of highly diffusive point defects during silicon plasma etching

The quantitative prediction and precise control of plasma-induced damage (PID) via high-energy ion bombardment during Si plasma etching for detailing the regions of amorphous, dangling bonds (DBs), and point defects (interstitials, vacancies, and clusters) are essential to realize the high performance of complementary metal-oxide-semiconductor (CMOS) devices. This study focused on the point defects of single Si interstitial (I1) and its cluster, particularly, distributed in regions deeper than those of amorphous and DBs, as PID. Numerical simulation models were proposed, where the I1 defects were first generated depending on etching conditions (types of gas, power, pressure, and bias) and were subsequently highly diffused through interaction among nearby other I1 defects, vacancies, and the Si interface. For Si trench etching with incident ion energy of 1200 eV, such a process resulted in the formation of tri-interstitial (I3) and tetra-interstitial (I4) clusters. The phenomena of reactive diffusions of I1 and its clusters dependent on the temperature of the n-type Si substrate were formulated. This formulation considered the following experimental results: (1). photoluminescence, along with the distance from the etched Si trench sidewall showing extensive distributions of the point defects over the 100 μm region and (2) in situ x-ray photoelectron spectroscopy on the B1s spectrum in the highly B-doped Si substrate for various x-ray irradiation angles, after Ar+ ion irradiation into the doped substrate as PID at temperatures of 25, −50, and −120 °C. By setting the low activation energy of less than 0.1 eV as the diffusion model parameter, corresponding to the diffusivity of an order of 10−4 cm2/s, the proposed model could reproduce not only the extensive distributions of I1 and I3 clusters as confirmed by the photoluminescence (PL) measurement, but also the absolute values of the I1 and I3 densities, as analyzed by deep-level transient spectroscopy. The results of the simulated I1 diffusion dependent on the wafer temperature of the n-type Si substrate using this model demonstrated that I1 diffusion could be suppressed and localized within the 4 nm region from the Si trench surface at an extremely low temperature of −150 °C. Further, this observation was found to be consistent with x-ray diffuse scattering analysis findings. Additional in situ after-treatment to remove the damaged layer, including localized I1 defects under the same temperature, resulted in the ultra-low PID. Therefore, cryogenic Si etching at very low temperatures exhibits considerable potential for not only improving the etched profile but also suppressing PID in realizing the high performance of advanced CMOS devices. This study provides us with valuable insights for developing new concepts of process module and device designs without requirement of annealing for the PID recovery.