Silicon Nanowire Gate‐All‐Around Cold Source MOSFET With Ultralow Power Dissipation: A Machine‐Learning‐Hamiltonian Accelerated Design

Abstract Exploring gate length scalability and enhancing performance in silicon‐based devices remain viable strategies to extend Moore's Law. However, these efforts have been hindered by deteriorative short‐channel effects and 60 mV dec −1 thermionic limitation of subthreshold swing ( SS ) at room temperature. To address these challenges, a gate‐all‐around (GAA) cold source field‐effect transistors (CSFETs) is designed based on the silicon nanowire (SiNW) with the characteristic of isolated bands, which is identified through a machine‐learning‐Hamiltonian accelerated high‐throughput search. The ab initio quantum transport simulations demonstrate that sub‐10‐nm SiNW CSFETs can exhibit excellent ballistic transport properties, meeting the International Technology Roadmap for Semiconductors (ITRS) criteria for high‐performance and low‐power devices. Thanks to the intrinsic cold source mechanism enabled by the isolated bands of the SiNW homojunction, the SS of SiNW CSFETs surpasses the “Boltzmann's tyranny”, thereby leading to superb gate controllability. The synergistic effects of the cold source and cold drain further reduce the average SS , enhancing the device's potential for ultralow power dissipation. Consequently, the energy‐delay product values are significantly comparable to those of carbon nanotube (CNT) FETs. The work offers a promising candidate for energy‐efficient solutions utilizing mainstream silicon fabrication processes.