FSMA: Fine-Grained Inter-Layer Scheduling and Mapping Co-Exploration Framework for Chiplet-Based DNN Accelerators

In modern computing environments, chiplet-based DNN accelerators have emerged as a promising technology for embedded systems. However, chiplet-based designs have led to complex topologies, non-uniform links, and inter-chiplet connections with lower bandwidth and higher power consumption, posing challenges to scheduling and mapping for enhancing system performance and energy efficiency. To effectively deploy DNN workloads, the paper introduced a fine-grained inter-layer scheduling and mapping co-exploration framework, FSMA, which is well-suited for chiplet-based DNN inference embedded systems. To maximize the optimization opportunities, an inter-layer scheduling and mapping encoding scheme centered on fine-grained multi-dimensional cut is proposed. To further explore the optimization space delimited by the encoding scheme, an exploration algorithm with the operators specifically designed is developed to modify the scheduling and mapping collaboration. Experimental results have proven the superiority of the proposed scheduling and mapping optimization for chiplet scenarios across diverse topologies and routing algorithms. Compared with the prior designs, FSMA achieves reductions of 47.05% and 28.9% in the energy-delay product (EDP) on average, respectively.