X-Shaped Thin-Film-Transistor Design for Minimizing Parasitic Capacitance in Back-Channel-Etched Structure for Displays

Back-channel-etched (BCE) thin-film transistors (TFTs) suffer from large gate-to-drain (C<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GD</sub>) and gate-to-source (C<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub>) parasitic capacitances, leading to increased power consumption and degraded display quality. This study proposed a novel TFT design that connects two short-channel-length (SCL) TFTs in series with an X-shaped node, reducing C<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GD</sub> and C<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> by 55%, in which the channel length was half that of a conventional TFT. Although the proposed TFT is based on an SCL structure, experimental results confirm that short-channel effects such as drain-induced barrier lowering and hot carrier stress are effectively mitigated. Additionally, power consumption analysis showed a 53% reduction in data and scan lines, demonstrating the potential for low-power displays.