A power/energy-efficient 8T SRAM with reduced minimum operation voltage

Abstract This paper aims to design a novel 8T SRAM, engineered to meet the requirements of low-power/energy portable devices. The proposed 8T SRAM bit cell integrates several innovative techniques, including the removal of leakage from the decoupled read path, the use of a single reading transistor, power-gating, and p-type transistor stacking within the latch core. These enhancements collectively result in superior performance metrics. The proposed 8T SRAM achieves a read static noise margin (RSNM) of 0.203 V and a write static noise margin (WSNM) of 0.270 V, representing improvements of 1.86 × and 2.41×, respectively, over the conventional 6T SRAM. Additionally, it demonstrates significant power efficiency, consuming 3.93 μW during read operations, 5.9 μW during write operations, and 16.07 nW in leakage power—reducing power consumption by at least 9.31%, 6.65%, and 8.95%, respectively, compared to state-of-the-art SRAM designs. A failure probability analysis was performed to determine the minimum operating voltage ( V DDmin ) of the proposed SRAM. The results show that the proposed 8T design lowers V DDmin from 710 mV (6T SRAM) to 430 mV, enhancing robustness in low-voltage operation. However, this improvement comes with a 1.42× increase in layout area compared to the 6T SRAM cell.