RRAM-Based In-Memory Stochastic Computing for Naïve Bayes Classifiers

A resistive random access memory (RRAM)-based in-memory stochastic computing (SC) scheme is proposed to address the limitation of representing small numbers in SC circuits, particularly for Naïve Bayes Classifiers (NBCs). The proposed scheme replaces multiplication with logarithmic summation, which is inherently realized through the logarithmic dependence of RRAM conductance and in-memory column-wise current accumulation. The scheme is evaluated using a fabricated RRAM array, demonstrating high classification accuracy, low hardware cost, and strong error tolerance. This work offers valuable insights for the design of SC circuits and supports the development of efficient edge computing systems.