Reliability Analysis of CFETs Under Various NBTI Conditions

This paper investigates the Negative-bias temperature instability (NBTI) effect in the p-type transistor of a CFET structure. Using a calibrated TCAD simulation framework, we modeled the PFET of CFET under various gate stress voltage <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\mathrm{V}_{\text{gstr}})$</tex> and temperature conditions to analyze its electrical degradation during both stress and recovery situations. This study provides insights into the reliability challenges of CFET devices and offer valuable guidance for future CFET technology.