Experimental Demonstration of Vertically Stacked Parallel Silicon Quantum Dots
We report the first experimental demonstration of a two-layer stacked silicon (Si) quantum dot (QD) device. At 300 K, distinct conduction humps indicate separate activation of the bottom and top channels, consistent with simulation results. At 4 K, Coulomb blockade peaks confirm single-hole transport in each layer. These findings validate a multi-layer QD device fabricated using a CMOS-compatible process, paving the way for higher-density quantum computing architectures.
Authors
- Junoh Kim (ORCID: https://orcid.org/0000-0002-0896-7561)
- Takuya Saraya (ORCID: https://orcid.org/0000-0002-3796-7747)
- Hiroshi Oka (ORCID: https://orcid.org/0000-0002-6571-3461)
- T. Mizutani (ORCID: https://orcid.org/0000-0002-2358-3945)
- Masaharu Kobayashi (ORCID: https://orcid.org/0000-0002-7945-6136)
- Takahiro Mori (ORCID: https://orcid.org/0000-0001-5899-1060)
- Toshiro Hiramoto (ORCID: https://orcid.org/0000-0001-9469-2631)
- Daiki Futagi
Institutions
- Italian Cultural Institute, Tokyo (JP)
- National Institute of Advanced Industrial Science and Technology (JP)
Publication Details
- Published
- 2025-06-08
- DOI
- https://doi.org/10.23919/snw65111.2025.11097254
- Primary Topic
- Semiconductor Quantum Structures and Devices
- Type
- article
- Field-Weighted Citation Impact
- 0.00