All-in-One Monolithic 3D Heterostructured Integration of BEOL-Complementary N-Si FinFET / P-CNFET for Smart Edge Processing
We report an all-in-one 3-tiers Monolithic 3D (M3D) architecture by integration of multi-functional CNFETs on dual-tiers Si FinFETs. The 1<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">st</sup>-tier consists of Si CMOS logic circuits, and CFET is formed by vertically stacking complementary N-type FinFET in the 2<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nd</sup>-tier and P-type CNFET in the 3<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rd</sup>-tier. In addition, Si/CNT CFETs have logic, sensing, and memory capabilities with potential for in-sensor computing and smart edge processing.
Authors
- Yanzhao Wei (ORCID: https://orcid.org/0000-0003-0372-2423)
- Feixiong Wang (ORCID: https://orcid.org/0000-0002-9129-9399)
- Huaxiang Yin (ORCID: https://orcid.org/0000-0001-8066-6002)
- Hongyang Huang (ORCID: https://orcid.org/0000-0001-5676-0621)
- Shuang Liu (ORCID: https://orcid.org/0000-0001-8148-1974)
- Yadong Zhang (ORCID: https://orcid.org/0000-0003-2861-7662)
- Yanqing Li (ORCID: https://orcid.org/0000-0002-3532-4254)
Institutions
- Institute of Microelectronics (SG)
- Institute of Microelectronics (CN)
Publication Details
- Published
- 2025-06-08
- DOI
- https://doi.org/10.23919/snw65111.2025.11097236
- Primary Topic
- Semiconductor materials and devices
- Type
- article
- Field-Weighted Citation Impact
- 0.00