Below 10A CMOS- Double CFETs (ↄc-FETs) with Dielectric-Wall-Stress by Isolation-Last Process for 0.0069 um² of SRAM-Cell Design

This paper presents the design and simulation of a novel CMOS structure, the Double-CFETs or ↄc-FETs, as a successor to the CFETs beyond 10A. The ↄc-FETs are realized by introducing a dielectric wall (DW) within the back-end-of-line (BEOL), employing an isolation-last process to effectively form 2 separated CFETs. The incorporated DW induces tensile strain along the ↄc-FETs channel-direction, resulting in an enhancement of the pFET, while causing a slight degradation in the nFET regarding Vth, off-state current, on-state current, and DIBL. Furthermore, standard logic cells and a 6T-SRAM cell composed of the ↄc-FETs have been simulated. We predict that the cell size of a 6T SRAM based on the ↄc-FETs can be reduced to 0.0069 μm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>. The ↄc-FETs were also implemented in a D Flip-Flop, performed at 5 GHz. These findings underscore the area-saving and competitive electrical characteristics of the ↄc-FETs, as a promising candidate for future CMOS nodes.