InAs/AlSb III-V NVM with High-Speed (5ns) Low-Power (1V) QW-Tunnel Program for 10-Year Storage by 2DEG-Enhanced Retention

This study introduces and simulates a novel non-volatile memory (NVM) device based on an InAs/AlSb heterostructure, featuring a quantum-confined channel between gate stacks and a tunnel-barrier resonant tunneling (TBRT) structure for electron storage. This architecture achieves high-speed (5 ns) and low-power (1V) programming via quantum well (QW) tunneling, leveraging a two-dimensional electron gas (2DEG) to enhance charge retention and enabling projected 10-year data retention. However, achieving reliable data storage necessitates a trade-off with erasing times, requiring <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$&gt; 1 \mu s$</tex> to remove electrons from the 2DEG. This work demonstrates the significant potential of this III-V NVM structure for future main-memory applications.