Poly-Si Nanosheet FETs with Vertical C-Shaped Channel Using Pulse Laser Crystallization

Poly-Si nanosheet FETs (NSFETs) with vertical C-shaped channel are experimentally demonstrated using pulse layer crystallization. The vertical channel shows Si (110) plane and better crystallization is accomplished using exposed-drain integration strategy. The poly-Si NSFETs have SS of 67.5 mV/decade, <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\boldsymbol{I}_{\text{OFF}}$</tex> of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$4.6\ \text{pA} / \mu \mathrm{m}$</tex>, and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$I_{\text{ON}} / I_{\text{OFF}}$</tex> of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$6.2\times 10^{6}$</tex>. The present process provides a new pathway for upper device fabrication in monolithic 3D (M3D) technology.

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Published
2025-06-08
DOI
https://doi.org/10.23919/snw65111.2025.11097229
Primary Topic
Thin-Film Transistor Technologies
Type
article
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article

Poly-Si Nanosheet FETs with Vertical C-Shaped Channel Using Pulse Laser Crystallization

Shujuan Mao, Xianglie Sun, Guilei Wang, Yongkui Zhang et al.
Thin-Film Transistor Technologies
article

Poly-Si Nanosheet FETs with Vertical C-Shaped Channel Using Pulse Laser Crystallization

Shujuan Mao, Xianglie Sun, Guilei Wang, Yongkui Zhang, Junfeng Li, Chao Zhao, Jun Luo, Jinbiao Liu, Huilong Zhu, Zhuo Chen
article en

Abstract

Poly-Si nanosheet FETs (NSFETs) with vertical C-shaped channel are experimentally demonstrated using pulse layer crystallization. The vertical channel shows Si (110) plane and better crystallization is accomplished using exposed-drain integration strategy. The poly-Si NSFETs have SS of 67.5 mV/decade, <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\boldsymbol{I}_{\text{OFF}}$</tex> of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$4.6\ \text{pA} / \mu \mathrm{m}$</tex>, and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$I_{\text{ON}} / I_{\text{OFF}}$</tex> of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$6.2\times 10^{6}$</tex>. The present process provides a new pathway for upper device fabrication in monolithic 3D (M3D) technology.

Institute of Microelectronics (SG), University Memory and Aging Center (US)
Affordable and clean energy
Openalex Percentile: Top 83%
Thin-Film Transistor Technologies
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Poly-Si Nanosheet FETs with Vertical C-Shaped Channel Using Pulse Laser Crystallization — Shujuan Mao, Xianglie Sun, et al. · (2025) | TGRS Research Map | TGRS