Integration of Optimized Superlattice HfO<sub>2</sub>/ZrO<sub>2</sub> Dielectric into High-Performance Superlattice SiGe/Si p-Type GAAFETs
This study investigated the impact of annealing temperature on superlattice HfO<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf>/ZrO<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> (SL-HZO) metal-insulator-metal and metal-insulator-semiconductor capacitors. A SL-HZO with a layer thickness of 0.5 nm exhibited ultrahigh dielectric constant and low equivalent oxide thickness at an annealing temperature of 450°C, attributed to the morphotropic phase boundary crystalline phase. This optimized condition was integrated into a superlattice SiGe/Si p-type gate-all-around field-effect transistor, achieving excellent subthreshold swing and a high on/off current ratio.
Authors
- Fu-Ju Hou (ORCID: https://orcid.org/0000-0001-8288-2542)
- Guang-Li Luo (ORCID: https://orcid.org/0000-0001-9429-4342)
- Yung‐Chun Wu (ORCID: https://orcid.org/0000-0001-9409-6792)
- Kai‐Ting Huang (ORCID: https://orcid.org/0000-0003-3138-3406)
- Heng-Jia Chang
- Tsai-Jung Lin
- Yi-Ju Yao (ORCID: https://orcid.org/0009-0000-7197-5495)
- Chen-You Wei (ORCID: https://orcid.org/0009-0005-5563-9690)
- Bo-Xu Chen
- Yu‐Min Fu
- Yung-Teng Fang
Institutions
- National Tsing Hua University (TW)
- Taiwan Semiconductor Manufacturing Company (Taiwan) (TW)
Publication Details
- Published
- 2025-06-08
- DOI
- https://doi.org/10.23919/snw65111.2025.11097212
- Primary Topic
- Semiconductor materials and devices
- Type
- article
- Field-Weighted Citation Impact
- 0.00