Design Optimization of SiC CMOS FinFET for High-Temperature Next-Generation SoC Logic Applications

In this study, we demonstrate a high-temperature-operable binary inverter through structural optimization of a SiC CMOS FinFET. The <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$V_{\text{th}}$</tex> and SS were optimized to achieve CMOS-compatible operation. The resulting FinFET-based binary inverter operates at 3.3V, exhibiting a max gain of 8.2 and noise margin of 0.92V even at temperatures up to 500K, confirming its robustness for high-temperature CMOS applications.