DIGITAL CLOCK DESIGN BASED ON PROTEUS SIMULATION SOFTWARE

In the context of the limitations of traditional timekeeping tools, the continuous progress of electronic and digital technologies, the increasingly diversified needs of different application scenarios, and the ever-increasing requirements of user experience, the research on digital clock circuit design has emerged and continues to develop. This digital clock circuit employs a cascaded configuration of 74160 adder counters to achieve sexagesimal counting for seconds and minutes, and twenty-four-ary counting for hours, thereby enabling the counting of hours, minutes, and seconds, which are displayed via seven-segment displays. Simulation verification was conducted using Proteus simulation software. The circuit operates stably within the timing range of 00:00:00 to 23:59:59. The second counter switches to the minute counter every 60 seconds, the minute counter switches to the hour counter every 60 minutes, and the hour counter automatically resets every 24 hours. This paper provides low-cost and easy to reproduce the simulation circuit, on the understanding and mastery of the principle of digital clock has a certain role in assisting, for the subsequent design of complex digital systems to lay the foundation.