Energy-Efficient GNRFET-Based Ternary Full Adder for Next-Generation Integrated Circuits

VDD/2.This middle point is labeled as "0.5" to represent the middle value.This third voltage level, the middle point VDD/2, minimizes the number of gates which makes connections in the circuit less complicated.

Publication Details

Journal
Journal of VLSI Circuits and Systems
Published
2025-01-01
DOI
https://doi.org/10.31838/jvcs/07.01.12
Primary Topic
Advancements in Semiconductor Devices and Circuit Design
Type
article
Field-Weighted Citation Impact
0.00
Controls
|||
ALL TIME
JAN
FEB
MAR
APR
MAY
JUN
JUL
AUG
SEP
OCT
article

Energy-Efficient GNRFET-Based Ternary Full Adder for Next-Generation Integrated Circuits

Journal of VLSI Circuits and Systems
Advancements in Semiconductor Devices and Circuit Design
article

Energy-Efficient GNRFET-Based Ternary Full Adder for Next-Generation Integrated Circuits

article en

Abstract

VDD/2.This middle point is labeled as "0.5" to represent the middle value.This third voltage level, the middle point VDD/2, minimizes the number of gates which makes connections in the circuit less complicated.

Journal of VLSI Circuits and SystemsVol. 7(1)
Affordable and clean energy
Openalex Percentile: Top 83%
Advancements in Semiconductor Devices and Circuit Design
DOIOpen Access PDFOpenAlex
AI Navigator

Ask Laika to Summarize, Analyze, and Connect papers live on the map.

Summarize Papers & Methodologies

Extract key findings, datasets, and comparative methods across publications.

Benchmark Rankings & Visual Analytics

Rank top research institutions, authors, funders, topics, and journals by Field-Weighted Citation Impact (FWCI) and paper volume with instant charts.

Connect Distant Disciplines

Bridge topological clusters on the map to find hidden collaborative intersections.

Energy-Efficient GNRFET-Based Ternary Full Adder for Next-Generation Integrated Circuits · Journal of VLSI Circuits and Systems (2025) | TGRS Research Map | TGRS