Adaptive VLSI Design Using Dynamic Voltage and Frequency Scaling (DVFS) for Low-Latency IoT Communication Networks

This paper presents the design of a comparator with low power, low offset voltage, high resolution, and rapid speed.The designed comparator is built on 45 flip CMOS technology and runs 4.2 samples per second at nominal voltage.It is a custom-made comparator for a highly linear 4-bit Flash A/D Converter (ADC).The outlined design can operate on a nominal supply of 1.8 V.The comparator offset voltage was elevated because of this mismatch.To compensate for the offset voltage, we followed a decent approach to design the circuits.Therefore, the offset voltage is reduced to 250.The designed comparator has a unity gain bandwidth of 4.2 and a gain of 72 at nominal PVT, which gives us a considerable measure of authority.The dynamic power consumption of the comparator is 48.7.The layout of this designed comparator has been implemented, and the area of the comparator is 12.3 15.75 .The results of pre-and post-layout simulations in various process, voltage, and temperature corners are shown.