Design and Analysis of On-Chip Reconfigurable SCVR With Wide Output Voltage Range for SoCs

A comprehensive framework for the analysis and design of reconfigurable two-phase switched-capacitor (SC) DC-DC converters is introduced. Initially, a generalized approach leveraging graph theory and network analysis is presented, enabling the enumeration of all possible ideal conversion ratios for a given SC converter topology. This methodology extends the performance boundaries of two-phase SC converters, leading to the proposal of a reconfigurable, two-phase SC DC-DC converter. The proposed converter incorporates a programmable, optimized switching configuration that enhances the number of achievable ideal conversion ratios for a fixed set of capacitors and switching states. This flexibility enables the converter to operate with high efficiency across a broad spectrum of operating conditions while achieving significantly high step-down conversion ratios. This work presents a reconfigurable, fully integrated, two-phase interleaved switched-capacitor voltage regulator (SCVR) with an on-die MIM capacitor intended for low-power system-on-chips (SoCs). High power density and efficiency are made possible in on-chip switched-capacitor (SC) converter implementations using MIM capacitors with a low bottom-plate parasitic. The charge-multiplier model for reconfigurable SCVR is investigated and verified through modeling and simulation. With varying power supplies of 1.24 V, 1.15 V and 1.03 V, a reconfigurable SCVR having four voltage conversion ratios (VCRs) has been designed to provide dynamic voltage scaling (DVS) of many-core microprocessors on a per-core basis. Further, the converter’s parasitic and charge-sharing losses are efficiently reduced by utilizing switch and frequency scaling techniques. The proposed SCVR is reconfigured into four gain topologies having VCRs 5:4, 4:3, 3:2 and 1:1 respectively. The nominal output voltage of the converter ranges from 0.6V to 1V, from three different power supplies. The proposed converter has a maximum load current of 625mA and a peak efficiency of 81.09%. Further, it delivers load current ranging from 200mA to 625mA with an efficiency greater than 70%. To validate the design, it is developed and simulated using a 22nm CMOS process. Matlab and PSpice simulation tools are used to verify the results.