A Unified Early-Warning AVFS Design With Path Activation-Aware Monitoring Point Optimization

This work proposes a unified early-warning adaptive voltage-frequency scaling (AVFS) system that offers a practical low-power solution for commercial IoT devices. First, a path activation-aware monitoring point optimization strategy is proposed to mitigate the risk of illegal voltage scaling. The strategy combines the path activation evaluation with the required timing guard band, reducing monitoring costs by 18.7%. Second, a delay-compensated dual-shadow monitor is developed and paired with a scalable monitoring window sizing methodology to monitor the timing of paths with memory-type endpoints, overcoming the limitation of monitoring only DFF-type endpoints. Third, a unified architecture that integrates both frequency and voltage scaling is presented to alleviate the problems of the off-chip voltage regulation. Fabricated in 40nm CMOS, a Cortex M0+ CPU with AVFS achieves voltage reductions between 15.4% and 29.5% and power savings ranging from 32.3% to 49.3% at 50-100MHz across SS/TT/FF corners.

Authors

Institutions

Publication Details

Journal
IEEE Solid-State Circuits Letters
Published
2025-01-01
DOI
https://doi.org/10.1109/lssc.2025.3593960
Citations
1
Primary Topic
Anomaly Detection Techniques and Applications
Type
article
Field-Weighted Citation Impact
2.48

Funders

Controls
|||
ALL TIME
JAN
FEB
MAR
APR
MAY
JUN
JUL
AUG
SEP
OCT
article

A Unified Early-Warning AVFS Design With Path Activation-Aware Monitoring Point Optimization

Junyi Qian, Li Cai, Weiwei Shan, Kaize Zhou et al.
1 citations
IEEE Solid-State Circuits Letters
Anomaly Detection Techniques and Applications
2.48
article

A Unified Early-Warning AVFS Design With Path Activation-Aware Monitoring Point Optimization

Junyi Qian, Li Cai, Weiwei Shan, Kaize Zhou, Haochang Zhi
article en
1 citations

Abstract

This work proposes a unified early-warning adaptive voltage-frequency scaling (AVFS) system that offers a practical low-power solution for commercial IoT devices. First, a path activation-aware monitoring point optimization strategy is proposed to mitigate the risk of illegal voltage scaling. The strategy combines the path activation evaluation with the required timing guard band, reducing monitoring costs by 18.7%. Second, a delay-compensated dual-shadow monitor is developed and paired with a scalable monitoring window sizing methodology to monitor the timing of paths with memory-type endpoints, overcoming the limitation of monitoring only DFF-type endpoints. Third, a unified architecture that integrates both frequency and voltage scaling is presented to alleviate the problems of the off-chip voltage regulation. Fabricated in 40nm CMOS, a Cortex M0+ CPU with AVFS achieves voltage reductions between 15.4% and 29.5% and power savings ranging from 32.3% to 49.3% at 50-100MHz across SS/TT/FF corners.

IEEE Solid-State Circuits LettersVol. 8
Southeast University (CN)
National Natural Science Foundation of China, National Key Research and Development Program of China
Openalex Percentile: Top 9%
Anomaly Detection Techniques and Applications
2.48
AI Navigator

Ask Laika to Summarize, Analyze, and Connect papers live on the map.

Summarize Papers & Methodologies

Extract key findings, datasets, and comparative methods across publications.

Benchmark Rankings & Visual Analytics

Rank top research institutions, authors, funders, topics, and journals by Field-Weighted Citation Impact (FWCI) and paper volume with instant charts.

Connect Distant Disciplines

Bridge topological clusters on the map to find hidden collaborative intersections.

A Unified Early-Warning AVFS Design With Path Activation-Aware Monitoring Point Optimization — Junyi Qian, Li Cai, et al. · IEEE Solid-State Circuits Letters (2025) | TGRS Research Map | TGRS