HALMF: High-performance Approximate Logarithmic Multiplier based on FPGA

To enhance the performance of computationally intensive intelligent applications, approximate multipliers leveraging error tolerance have been widely explored for improving the power and performance efficiency of computing units. FPGAs, with their reconfigurability and short development cycles, offer a flexible platform for deploying such designs. This paper presents a novel methodology for designing FPGA-based approximate logarithmic multipliers by converting multiplier to adder and shifter to reduce the hardware resource. By eliminating insignificant bit detection, the area and power of detecting circuit are reduced. Fraction adder is restructured to support the parallel computation in lower bits to decrease latency, and a general compensation method is proposed to enhance accuracy. Compared to the exact multiplier, our proposed design reduces power, delay, and area by 49.63%, 1.97%, and 50.70%, respectively. Application-level evaluations confirm that the proposed designs offer better accuracy-hardware trade-off than other approximate designs.