Development of Quadruple Interlinked Latch-Based 10T and 12T SRAM Cells for Durable Terrestrial Solutions

This paper introduces the design of quadruple cross-coupled storage cells (QUCCE) in both 10T and 12T configurations, utilizing 130 nm CMOS technology. These QUCCE-based designs achieve the lowest critical charge comparable to unadventurous 6T SRAM. When associated to advanced SRAM architectures, they exhibit competitive or enhanced resilience to soft errors, improved timing performance, and superior read and grip static noise margins. The QUCCE 10T configuration maintains comparable or lower area and leakage power, making it well-suited for high-density SRAMs operating at nominal supply voltage. Additionally, the QUCCE 12T achieves more than a 50% reduction in read access time compared to predictable reference cells, including 6T SRAM, making it an excellent choice for high-speed applications. It also provides a strong read margin—second only to the conventional 8T—when assessed based on the μ/σ ratio in the near-threshold voltage range, with minimal write failures. These advantages make the QUCCE 12T a highly encouraging candidate for future low-voltage, extremely dependable ground-based applications.