Partition Matching Maximum Zero-Sum Algorithm to Address VLSI Thermal Placement Issues

In this paper, we address the thermal placement problem for gate arrays within the realm of VLSI physical design. Given the increasing compaction density and power consumption associated with System-on-Chip (SoC) designs managing thermal effects at the chip level has become increasingly critical uneven temperature distribution can lead to discrete hotspots. To address this issue, we utilize a Matrix Fusion Technique (MFT) formulation for Standard Cell Placement in VLSI Design. We construct a maximum zero sum partition matching (MZSPM) algorithm to minimize the neighbourhood area of heat generation and minimize the number of hotspots along with considerable reduction in the magnitude of temperature generation. By applying the proposed method, we effectively lower the temperature localization challenges in VLSI physical design automation. We have validated that the proposed algorithm, which utilizes randomly generated numbers, yields promising results.