A CDS-compensated RC Relaxation Oscillator for Clock Generation in Single-Chip IoT Devices

Modern System-on-Chips for emerging smart sensing and IoT applications require on-chip integration of efficient oscillators to generate the system clock signal. To generate clock signals in the MHz range, relaxation oscillators are ideal candidates, due to their compactness and frequency tunability. However, to mitigate jitter-related issues (especially the long-term accumulated jitter, originating from flicker noise sources), dedicated circuit techniques have to be implemented. In this work, we present an RC relaxation oscillator automatically applying correlated double sampling compensation to the comparator noise. Experimental measurements of a 10-MHz prototype fabricated in 0.18-μm CMOS, occupying an area of 0.0042 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>, demonstrated a power-efficiency figure of merit of 4.59 μW/MHz and standard deviation of the accumulated jitter equal to 0.3 cycles over 10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> observed cycles. These results prove suitability of the proposed oscillator for system-level synchronization of single-chip IoT devices and precise clock generation for asynchronous serial communication protocols.