An Investigation of Magnitude Comparator Design using Intermediate Zero-Free Binary Signed-Digit Representation

Signed-digit number systems have been found to be more supportive to achieve higher speed for addition / subtraction, multiplication, typical digital filter design and some other arithmetic operations. Accordingly signed-digit number systems seem to be more suitable for digital signal processing, image processing and cryptographic architectures. Amongst of various classes of signed-digit number systems the binary signeddigit number system has been studied most widely. However, in binary signed-digit arithmetic some operations appear to be quite complex. In particular, the straightforward approaches for magnitude comparator design are too complex. As a remedy canonical signed-digit number system-based magnitude compactor design has been recently proposed. Synchronically a typical representation of binary signed-digit number system, called the intermediate-zero-free binary signed-digit representation, has been introduced and this representation has been found promising to address some complex problems, including sign-detection, reverse conversion and overflow handling, in a more efficient manner. Arithmetic investigations are carried out in this paper shows that based on divide-andconquer strategy a novel magnitude comparator can be designed employing the intermediate zero-free binary signed-digit representation. Compared to its known contender, the proposed comparator can process $50 \%$ larger inputs. In addition, the proposed comparator attains logarithmic time complexity whereas its said contender involves linear time complexity.