Hybrid Digital Acquisition System Architecture Integrating ASIC-Based Fine Time Resolution With FPGA-Based Coarse Time Resolution

Digital acquisition systems are crucial in fields such as high-energy physics, communications, medical imaging, industrial control, radar, and lidar technologies due to their high precision, rapid response, and ability to handle time-sequenced events. These systems are typically implemented using either field-programmable gate arrays (FPGAs) or application-specific integrated circuits (ASICs). FPGA-based high-precision digital acquisition systems often utilize the FPGA’s carry chain. However, the non-uniform delay inherent in the carry chain can affect measurement accuracy. Conversely, ASIC-based systems generally require transferring time tags generated by the ASIC to an FPGA for subsequent processing. Given certain transmission capacities, increasing the number of coarse time bits necessitates reducing the number of fine time bits, thereby decreasing resolution, or reducing the number of events transmitted per unit time. This paper proposes a novel digital acquisition system architecture based on fine time measurement using an ASIC and coarse time measurement using an FPGA. This architecture combines the strengths of both ASICs and FPGAs, enabling high-precision event measurement over a wide range with a high counting rate. Additionally, a method for relative time tag operation based on this scheme is proposed. Finally, a prototype is designed and tested using ASIC (TDC-GPX2) and Altera’s Cyclone 4 series FPGA (EP4CE75F23I7N). This prototype features three input channels and one reference input channel, achieving a least significant bit (LSB) of 20 ps, a measurement accuracy of 30 ps, a measurement range of 430 s, an integral nonlinearity of [-3, 1.3] LSB, and a differential nonlinearity of [-0.6, 0.7] LSB. Long-term stability tests over 21 hours showed a peak-to-peak variation of 76 ps. Temperature stability tests conducted within the range of 25-65 °C indicated a peak-to-peak variation of 13 ps. These results demonstrate that the digital acquisition system exhibits excellent long-term and temperature stability.

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Journal
IEEE Transactions on Instrumentation and Measurement
Published
2025-01-01
DOI
https://doi.org/10.1109/tim.2025.3593574
Primary Topic
Advancements in PLL and VCO Technologies
Type
article
Field-Weighted Citation Impact
0.00

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article

Hybrid Digital Acquisition System Architecture Integrating ASIC-Based Fine Time Resolution With FPGA-Based Coarse Time Resolution

Mingjia Shangguan, Zaifa Lin, Fuqing Cao
IEEE Transactions on Instrumentation and Measurement
Advancements in PLL and VCO Technologies
article

Hybrid Digital Acquisition System Architecture Integrating ASIC-Based Fine Time Resolution With FPGA-Based Coarse Time Resolution

Mingjia Shangguan, Zaifa Lin, Fuqing Cao
article en

Abstract

Digital acquisition systems are crucial in fields such as high-energy physics, communications, medical imaging, industrial control, radar, and lidar technologies due to their high precision, rapid response, and ability to handle time-sequenced events. These systems are typically implemented using either field-programmable gate arrays (FPGAs) or application-specific integrated circuits (ASICs). FPGA-based high-precision digital acquisition systems often utilize the FPGA’s carry chain. However, the non-uniform delay inherent in the carry chain can affect measurement accuracy. Conversely, ASIC-based systems generally require transferring time tags generated by the ASIC to an FPGA for subsequent processing. Given certain transmission capacities, increasing the number of coarse time bits necessitates reducing the number of fine time bits, thereby decreasing resolution, or reducing the number of events transmitted per unit time. This paper proposes a novel digital acquisition system architecture based on fine time measurement using an ASIC and coarse time measurement using an FPGA. This architecture combines the strengths of both ASICs and FPGAs, enabling high-precision event measurement over a wide range with a high counting rate. Additionally, a method for relative time tag operation based on this scheme is proposed. Finally, a prototype is designed and tested using ASIC (TDC-GPX2) and Altera’s Cyclone 4 series FPGA (EP4CE75F23I7N). This prototype features three input channels and one reference input channel, achieving a least significant bit (LSB) of 20 ps, a measurement accuracy of 30 ps, a measurement range of 430 s, an integral nonlinearity of [-3, 1.3] LSB, and a differential nonlinearity of [-0.6, 0.7] LSB. Long-term stability tests over 21 hours showed a peak-to-peak variation of 76 ps. Temperature stability tests conducted within the range of 25-65 °C indicated a peak-to-peak variation of 13 ps. These results demonstrate that the digital acquisition system exhibits excellent long-term and temperature stability.

IEEE Transactions on Instrumentation and MeasurementVol. 74
Xiamen University (CN)
National Natural Science Foundation of China, Fundamental Research Funds for the Central Universities
Affordable and clean energy
Openalex Percentile: Top 83%
Advancements in PLL and VCO Technologies
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