T-Type Phase Shifter with C-L-C Structure Using 28-nm FD-SOI CMOS Process for 5G FR2 Applications

In this study, we design a T-type passive phase shifter using 28-nm FD-SOI CMOS process for 5G FR2 applications. In the passive phase shifter, the size of the total phase shifter is determined by the number of used spiral inductors. Therefore, in order to reduce the area of the overall phase shifter, in this study, phase shifter is designed using a C-LC structure that can reduce the number of inductors required compared to the L-C-L structure. In order to secure the overall unity of the phase shifter, all bits constituting the phase shifter used the same circuit structure. In this study, equivalent circuits in shift and pass states are analyzed to implement 5.625°, 11.25°, 22.5°, 45°, and 90°-bits using the schematic of unit-bits. 180°-bit is implemented by connecting two 90°-bits. The phase shifter of this study is designed with a single-ended structure to reduce the chip area. The operating frequency range of the designed phase shifter is set from 26.5 GHz to 29.5 GHz. The RMS phase error of the designed phase shifter is less than 8.75°. The chip size including the test pads is 1110 × 353 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>, and the core size is 930 × 250 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>.