Ka-Band Low-Noise Amplifier with Active Inductor Using 28-nm FD-SOI CMOS Process for 5G FR2 Applications

In this study, we design a low-noise amplifier using 28-nm FD-SOI CMOS process for 5G FR2 applications. Considering the connection with the antenna or SPDT switch, a low-noise amplifier is designed with a single-ended structure. A three-stage structure is applied to achieve sufficient power gain. To improve the noise figure, the inductive source degeneration technique is applied to the first stage. RC-feedback technique is applied to the second stage. The power gain flatness of the entire low-noise amplifier is adjusted through the resonance between the RC-feedback and the inductor of the second stage. In particular, the resonance frequency is set from the target frequency band to the low frequency region, and the power gain in the low frequency region is adjusted by adjusting the resistor of RC-feedback. Because the third stage has little effect on the noise figure of the entire low-noise amplifier, an active inductor is used to reduce the chip area of the low-noise amplifier. The power gain of the designed low-noise amplifier is higher than 24.8 dB in the 27 GHz to 30 GHz range. The K-factor is unconditionally stable as it is higher than 1 in all frequency range. In the operating frequency range of 27 GHz to 30 GHz, the noise figure is less than 3.12 dB. The chip size of the designed low-noise amplifier is 0.72  0.70 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>, and the core size is 0.42  0.41 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>.