Design of an FPGA-Based High-Efficiency YOLO Accelerator

To address the challenges of high power consumption and resource utilization when deploying YOLO algorithms in embedded systems, this study presents an FPGA-based hardware accelerator for an enhanced YOLOv4-Tiny architecture. First, we optimize the algorithm by replacing the Darknet53 backbone with GhostNet, substituting the original SE attention mechanism with CA (Coordinate Attention), and implementing dynamic hybrid quantization. These modifications significantly reduce computational complexity while maintaining detection accuracy, with rigorous training conducted on high-performance computing platforms. Second, we implement a dedicated hardware accelerator on FPGA that employs pipeline parallelism, loop unrolling, and ping-pong buffering strategies to maximize throughput for convolution and pooling operations. Finally, we design and evaluate a complete embedded vision system prototype. Experimental results demonstrate that the proposed accelerator achieves total power consumption of 3.06 W at 200 MHz operating frequency, delivering energy efficiency of 18.39 GOPS/W. Compared with conventional CPU implementations, the system shows 40.86× improvement in energy efficiency, while outperforming GPU platforms by 15.74× for equivalent algorithmic tasks. This work establishes a practical framework for efficiently deploying deep learning-based object detection in resource-constrained edge computing scenarios.