A 15-30 GHz Asymmetric SPDT Switch with Stacked Transistors Using 65-nm CMOS Process for Power-Handling Capability

This paper presents a 15 - 30 GHz single-pole double-throw (SPDT) switch using a 65 nm RF CMOS process for power handling capability. We propose a SPDT switch using asymmetric structure and the stacked transistor topology. SPDT switch requires high isolation, low insertion losses in both transmit and receive mode and high power-handling capability in transmit mode. For increasing the isolation, we used inductors which resonate with off-state transistors and stacked the transistors for high-power capability. At 15 – 30 GHz, the isolations in the Tx and Rx modes are simulated higher than 33.90 dB and 23.68 dB. Insertion loss is lower than 1.7 dB and 2.1dB in Tx and Rx mode, respectively. The input 1-dB compression points (IP<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1dB</inf>) are 22.88 dBm and 8.61 dBm in Tx and Rx mode, respectively. The core size of the designed circuit is 0.082mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>.