On the Design of Junction Termination for 4H-SiC High-Voltage Devices

Junction termination design has become a crucial process in ultrahigh-voltage 4H-SiC device design since it enhances the reliability and ensures that the device can reach the designed breakdown voltage. In this work, we review the blocking performances, fabrication considerations and area efficiencies of several typical termination structures widely used for ultrahigh-voltage 4H-SiC devices, and aim to optimize the termination design of next generation devices, focusing on improved termination efficiency, simultaneous design of breakdown voltage and surface field without introducing extra fabrication complexity and costs. The relationship between area efficiency, surface electric field and breakdown voltage is first described, indicating that improving the uniformity of electric field at the SiC/oxide interface is essential to improve the area efficiency. A buried termination structure, where implanted zones are buried under a thin field buffer layer is proposed to obtain a nearly rectangular field distribution at the SiC/oxide interface. The termination pattern is then directly scaled without any iterative design process to optimize the termination area, and the simulation results show that the field distribution can be mostly preserved. Optimization and limitations that are related to fabrication and design considerations are also addressed in the end.