Differential Injection Locked Frequency Divider With Dual Darlington Pairs for Wideband ÷4 Frequency Division in CMOS

This paper presents a 4.08 mW injection-locked frequency divider (ILFD) achieving division-by-4 with a 21.3% locking range (16.4-20.3 GHz) in 65 nm CMOS. The design employs dual CMOS Darlington pairs in a fully differential injection topology, simultaneously enhancing trans-conductance, switching speed, and power efficiency. Key innovations include a high-transit frequency (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$f_{T}$ </tex-math></inline-formula>) topology for robust high-frequency division and optimized harmonic rejection. Measured results show consistent 12 dB phase noise reduction (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$20\cdot \mathbf {log_{10}(4)}$ </tex-math></inline-formula>) across offsets up to 1 MHz, with harmonic rejection of 23.4 dB (3rd) and 49.3 dB (2nd) at 16.4 GHz. Competitive figures of merit of 0.95 GHz/mW and 19.4 GHz2/mW demonstrate state-of-the-art efficiency.