Design and Analysis of 8x8 Multiplier using 2:1 Multiplexer based Adder

This paper presents the design and analysis of an 8X8 multiplier utilizing a 2:1 multiplexer-based adder. By leveraging multiplexers for the addition of partial products, the proposed architecture simplifies the multiplication process, reducing complexity and power consumption while enhancing speed. This innovative approach offers a promising solution for efficient arithmetic operations in digital systems, paving the way for advancements in many applications, including digital signal processing and computer graphics. The proposed design of 8x8 multiplier using 2:1 multiplexer based on adder reduces a path delay by 31%,cpu time by 33% and real time to XST completion by 33%, area increased by 28%,power increased by 18% in comparision with 8x8 multiplier using full adder was created using the Xilinx Design Suite 14.2 and simulated using Modelsim.