Efficient VLSI Architecture for OTFS-MIMO Transceiver in Multipath Fading Channels

Orthogonal Time Frequency Space (OTFS) modulation has emerged as a promising technique for next-generation wireless communication systems, offering superior performance in high-mobility environments compared to traditional OFDM. However, implementing OTFS in a Multiple-Input Multiple-Output (MIMO) transceiver under multipath fading conditions poses significant computational and hardware complexity challenges. This paper presents a low-complexity VLSI architecture for an OTFS-MIMO transceiver optimized for real-time processing in multipath fading channels. The proposed design leverages efficient signal processing techniques, hardware-friendly algorithms, and optimized resource utilization to achieve high throughput and low latency. The architecture is implemented and synthesized on FPGA/ASIC platforms to evaluate performance metrics such as area, power, and processing speed. Simulation results demonstrate that the proposed design achieves significant improvements in energy efficiency and computational complexity while maintaining robust communication performance in dynamic wireless environments. This work provides a practical solution for integrating OTFS-MIMO in future high-speed wireless communication systems.