Shannon Adder-based 8×8 Multiplier with Power and Error Optimization

A device with a longer battery life is preferable than one that uses less power. The goal of this paper is to implement 8*8-bit multiplier with reduced power consumption using carry-skip technique with provision of Fault tolerant Shannon based full adder. These are multiples which form basic components in the development of circuits and systems hence their enhancement in power and performance is crucial in enhanced development and high-speed applications. These issues are masked by the here proposed seven-layer pipeline architecture that increases the through-put frequency and on the same note decrease the number of switch requirements hence the dynamic power consumption. This architecture highlighted in the current paper is implemented in 90 nm CMOS technology their functionalities are modeled using Cadence Xcelium tool to obtain waveforms for their cycle accurate functional simulation in Sim Vision, they also have to implement architectures. The results below imply that the intended compare-output module has done the right job given the input patters and that the pipeline timings have been as planned. Thus, the provided multiplier has advantages compared to the standard design from the point of view of power consumption and searching for the arithmetic level fault detection. These characteristics make the Schmitt circuit desirable for its use in the modern age VLSI systems such as low power dissipation, high reliability and high-speed arithmetic calculations.