High-Reliability Design Based on Bit-Level Repair Techniques

Traditional memory technologies are gradually difficult to meet the demands of high-reliability applications such as automotive electronics and aerospace systems. Spin-transfer torque magnetic random-access memory (STT-MRAM) has emerged as a promising alternative due to its fast read/write speed, high endurance, and full compatibility with CMOS processes. However, the unique physical properties of STT-MRAM pose challenges including hard errors (e.g., shorts) and various types of soft errors. To address these issues, this paper proposes a high-reliability design based on bit-level repair, allowing defective bits to be repaired through dedicated conversion circuits. This approach supports both hard errors repair prior to chip fabrication and real-time repair during the product's operational lifetime,With minimal redundancy and low design complexity, the proposed method significantly improves device endurance and yield.