Enhanced TransUNet Framework for Predicting Static IR Drop and Chip Routability

As semiconductor processes advance, the power delivery network (PDN) increasingly affects the power supply from the pads to the cells. Significant IR drops in standard cells can lead to timing violations, while suboptimal PDN topologies can lead to increased congestion. Together, these factors degrade overall chip performance and reliability. To accelerate design iteration, accurately and efficiently predicting unevenly distributed IR drop and congestion, especially in hotspot areas, has become a critical challenge. This article introduces an enhanced TransUNet-based framework for distribution-aware static IR drop and congestion prediction, treating both problems as separate but related image prediction tasks. Such an abstraction preserves the IR drop and congestion distribution patterns on the original real physical layout and retains local hot spots. Our proposed framework leverages image classification techniques to model IR drop prediction as a spatial pattern recognition task, effectively addressing the long-tail distribution in different regions. To enhance hotspot prediction, we incorporate wavelet transform and transformer-based analysis to enable multiscale feature fusion. In the open-source CircuitNet dataset, our method predicts static IR drop with a mean absolute error( MAE ) of 0.374 mV and a maximum error rate( Err m ) of 18.7%, reducing MAE and Err m by 77.4% and 79.2%, respectively, compared to the state-of-the-art method, all within 100 ms. The congestion prediction evaluations show 65.3% lower NRMSE scores and 18.4% higher SSIM scores relative to the existing SOTA approach. Our approach accurately and reliably predicts long-tail distributions and localized hotspots in both IR drop and congestion tasks.