DVIC: dynamic table-based randomization scheme for L1 cache

With the development of modern microprocessor architectures, cache-side channel attacks have become an increasingly serious security threat. In recent years, RISC-V processors have garnered significant attention, yet research on cache security for RISC-V processors is still in its infancy. To address this, this paper proposes a novel dynamic virtual indexed cache scheme, DVIC, which aims to enhance the security of the L1 cache for RISC-V processors. DVIC effectively disrupts the deterministic mapping relationship between memory addresses and cache set indexes by introducing a randomization mechanism based on dynamic tables. This significantly improves the system's resilience against cache-side channel attacks, such as Evict-Reload. We implemented DVIC on the Chipyard platform and conducted a comprehensive evaluation using the BOOM v3 processor. The experimental results demonstrate that DVIC provides robust security while incurring only minimal performance loss and resource overhead. This work offers new insights for designing secure and efficient cache systems for RISC-V processors.