A low-power and high-stability phase-locked loop with dynamic charge pump in wide frequency range applications

This paper presents a low-power and high-stability phase-locked loop designed for wide frequency ranges, optimized for low power consumption and compact area. Implemented in a 40nm CMOS process, the proposed PLL operates with input frequency from 9.6 MHz to 16 MHz and output frequency from 48 MHz to 144 MHz. The design includes a dynamic charge pump to adapt to varying division ratio, ensuring stable operation across a wide frequency range. The PLL also utilizes a current-controlled voltage oscillator to reduce the value of the tune sensitivity. The PLL, incorporating these advanced designs, achieves good stability in the operating frequency range and achieving a low power consumption of 0.239 mW.