Testing the acceleration and optimization of deep reinforcement learning algorithms in intelligent control using Zynq SoC platform

The Q learning algorithm faces the problems of low computing efficiency and insufficient resource utilization in intelligent control applications. Under the Zynq SoC platform, it is necessary to overcome the contradiction between the high complexity of the algorithm and the limitation of hardware resources to achieve algorithm acceleration and optimization. This paper makes full use of the unique architecture of the Zynq SoC platform, integrating high-performance ARM Cortex-A series processors and flexible FPGA (field programmable gate array) logic units. The Q learning algorithm is divided into the processing system (PS) part and the programmable logic (PL) part. The PS part is responsible for the overall scheduling, strategy update and low-complexity computing tasks of the algorithm; while the PL part uses the programmable logic resources of the FPGA to focus on the key computing tasks in the acceleration algorithm. In the process of hardware accelerator design, the characteristics of intelligent control application scenarios are specially considered, and matrix operations and tensor calculations are optimized. In the process of software development, efficient data transmission between PS and PL accelerators is guaranteed. The algorithm execution time under the Zynq SoC platform is lower than that of traditional CPUs. In terms of throughput, the average throughput of the Zynq SoC platform is 1181.9B/s, which is higher than the 883B/s of traditional CPUs. In terms of resource utilization, the maximum value of the Zynq SoC platform reaches 85%. These data fully demonstrate the unique advantages of the Zynq SoC platform in handling complex intelligent control tasks, which can significantly improve algorithm performance, reduce energy consumption, and enhance system stability and reliability.